SIM Bus Clock Control and Generation
Addr.
$FE04
Register Name
Read:
Interrupt Status Register 1
Write:
(INT1)
Reset:
Read:
Interrupt Status Register 2
Write:
(INT2)
Reset:
Read:
Interrupt Status Register 3
Write:
(INT3)
Reset:
Bit 7
0
R
0
IF14
R
0
0
R
0
6
5
IF5
IF4
R
R
0
0
0
0
R
R
0
0
0
0
R
R
0
0
= Unimplemented
4
IF3
R
0
0
R
0
0
R
0
3
0
R
0
0
R
0
0
R
0
R
2
IF1
R
0
0
R
0
0
R
0
= Reserved
1
0
R
0
0
R
0
0
R
0
Bit 0
0
R
0
0
R
0
IF15
R
0
$FE05
$FE06
Figure 5-2. SIM I/O Register Summary
5.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, OSCOUT, as shown in
FROM
OSCILLATOR
FROM
OSCILLATOR
2OSCOUT
OSCOUT
SIM COUNTER
÷
2
BUS CLOCK
GENERATORS
SIM
Figure 5-3. SIM Clock Signals
5.2.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (2OSCOUT) divided by four.
5.2.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 2OSCOUT cycle POR time-out has completed. The RST
pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the
time-out.
5.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This
time-out is selectable as 4096 or 32 2OSCOUT cycles. (See
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
51
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
