SIM Counter
5.3.2.5 LVI Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
DD
voltage falls to the LVI
trip voltage V
TRIP
. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RSTB) is held low while the SIM counter counts out 4096 2OSCOUT cycles. Sixty-four 2OSCOUT cycles
later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The
SIM actively pulls down the (RSTB) pin for all internal reset sources.
5.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of 2OSCOUT.
5.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
5.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a one, then the stop recovery is reduced from the normal delay of 4096
2OSCOUT cycles down to 32 2OSCOUT cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal applications should use the full
stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).
5.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See
for details.) The SIM counter is
free-running after all reset states. (See
for counter control and
internal reset recovery sequences.)
5.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
5.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
flow charts the handling of system interrupts.
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
55
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
