Freescale Semiconductor, Inc.
3.5 Instruction Set
Refer to Table 3-2, which shows all the M68HC11 instructions in all possible address-
ing modes. For each instruction, the table shows the operand construction, the number
of machine code bytes, and execution time in CPU E-clock cycles.
Table 3-2 Instruction Set (Sheet 1 of 7)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Operand Cycles
Condition Codes
Opcode
1B
S
—
X
—
H
I
N
Z
V
C
ABA
Add
A + B
A
INH
—
2
∆
—
∆
∆
∆
∆
Accumulators
ABX
ABY
Add B to X
Add B to Y
IX + (00 : B)
IY + (00 : B)
A + M + C
IX
IY
A
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
3A
3A
89 ii
99 dd
B9 hh ll
A9 ff
A9 ff
C9 ii
D9 dd
F9 hh ll
E9 ff
E9 ff
8B ii
9B dd
BB hh ll
AB ff
AB ff
CB ii
DB dd
FB hh ll
EB ff
—
—
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
∆
—
—
∆
—
—
∆
—
—
∆
18
18
18
18
18
18
18
ADCA (opr) Add with Carry
to A
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
ADCB (opr) Add with Carry
to B
B + M + C
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
∆
0
0
∆
∆
∆
ADDA (opr)
ADDB (opr)
Add Memory
to A
A + M
A
B
Add Memory
to B
B + M
2
3
4
4
5
∆
∆
IND,X
IND,Y
EB ff
ADDD (opr) Add 16-Bit to D D + (M : M + 1)
D
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
C3 jj kk
D3 dd
F3 hh ll
E3 ff
E3 ff
84 ii
94 dd
B4 hh ll
A4 ff
A4 ff
C4 ii
D4 dd
F4 hh ll
E4 ff
E4 ff
78 hh ll
68 ff
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
6
6
7
—
—
—
—
∆
ANDA (opr)
ANDB (opr)
ASL (opr)
AND A with
Memory
A • M
B • M
A
B
A
A
A
A
A
B
B
B
B
B
—
—
∆
AND B with
Memory
18
18
Arithmetic
Shift Left
0
68 ff
b7
b0
C
ASLA
ASLB
Arithmetic
Shift Left A
A
B
INH
INH
INH
48
58
05
—
2
2
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
∆
∆
∆
∆
∆
∆
0
0
b7
b7
b0
b0
C
C
Arithmetic
Shift Left B
—
—
ASLD
Arithmetic
Shift Left D
∆
∆
∆
∆
0
b7A b0 b7 B b0
C
ASR
Arithmetic
Shift Right
EXT
IND,X
IND,Y
77 hh ll
67 ff
67 ff
6
6
7
∆
∆
∆
∆
18
b7
b7
b7
b0
b0
b0
C
C
C
ASRA
ASRB
BCC (rel)
Arithmetic
Shift Right A
A
B
INH
INH
REL
47
—
2
2
3
∆
∆
∆
∆
Arithmetic
Shift Right B
57
—
∆
∆
∆
∆
Branch if Carry
Clear
? C = 0
24 rr
—
—
—
—
CENTRAL PROCESSING UNIT
3-8
TECHNICAL DATA
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