Freescale Semiconductor, Inc.
Table 3-2 Instruction Set (Sheet 2 of 7)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Operand Cycles
Condition Codes
Opcode
S
X
H
I
N
Z
V
C
BCLR (opr)
Clear Bit(s)
M • (mm)
M
DIR
IND,X
IND,Y
15 dd mm
1D ff mm
1D ff mm
6
7
8
—
—
—
—
∆
∆
0
—
(msk)
18
BCS (rel)
BEQ (rel)
BGE (rel)
BGT (rel)
BHI (rel)
BHS (rel)
Branch if Carry
Set
Branch if =
Zero
Branch if ∆
Zero
? C = 1
? Z = 1
REL
REL
REL
REL
REL
REL
25 rr
27 rr
2C rr
2E rr
22 rr
24 rr
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
? N V = 0
? Z + (N V) = 0
? C + Z = 0
? C = 0
Branch if >
Zero
Branch if
Higher
Branch if
Higher or
Same
BITA (opr)
Bit(s) Test A
with Memory
A • M
A
A
A
A
A
IMM
DIR
EXT
IND,X
IND,Y
85 ii
—
—
—
—
∆
∆
0
—
2
3
4
4
5
2
3
4
4
5
95 dd
B5 hh ll
A5 ff
18
18
A5 ff
BITB (opr)
Bit(s) Test B
with Memory
B • M
B
B
B
B
B
IMM
DIR
EXT
IND,X
IND,Y
C5 ii
—
—
—
—
∆
∆
0
—
D5 dd
F5 hh ll
E5 ff
E5 ff
BLE (rel)
BLO (rel)
BLS (rel)
Branch if ∆
Zero
? Z + (N V) = 1
? C = 1
REL
REL
REL
2F rr
25 rr
23 rr
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
3
3
Branch if
Lower
Branch if
Lower or
Same
? C + Z = 1
BLT (rel)
BMI (rel)
BNE (rel)
Branch if <
Zero
Branch if
Minus
Branch if not =
Zero
? N V = 1
? N = 1
REL
REL
REL
2D rr
2B rr
26 rr
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
3
3
? Z = 0
BPL (rel)
BRA (rel)
Branch if Plus
? N = 0
? 1 = 1
REL
REL
2A rr
20 rr
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
3
6
7
8
Branch Always
BRCLR(opr)
Branch if
Bit(s) Clear
DIR
IND,X
IND,Y
13 dd mm rr
1F ff mm rr
1F ff mm rr
? M • mm = 0
(msk)
(rel)
18
Branch Never
REL
21 rr
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRN (rel)
BRSET(opr)
(msk)
? 1 = 0
? (M) • mm = 0
3
Branch if Bit(s)
Set
DIR
IND,X
IND,Y
12 dd mm rr
1E ff mm rr
1E ff mm rr
6
7
8
6
7
8
(rel)
18
18
BSET (opr)
(msk)
Set Bit(s)
DIR
IND,X
IND,Y
14 dd mm
1C ff mm
1C ff mm
—
—
—
—
∆
∆
0
—
M + mm
M
Branch to
Subroutine
Branch if
Overflow Clear
REL
REL
REL
INH
8D rr
28 rr
29 rr
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
—
—
—
∆
—
—
—
∆
—
—
—
∆
BSR (rel)
BVC (rel)
BVS (rel)
CBA
See Figure 3–2
? V = 0
6
3
3
2
Branch if
Overflow Set
Compare A to
B
? V = 1
11
—
A – B
Clear Carry Bit
INH
INH
0C
0E
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
0
CLC
CLI
0
0
C
I
2
2
Clear Interrupt
Mask
—
Clear Memory
Byte
EXT
IND,X
IND,Y
7F hh ll
6F ff
6F ff
—
—
—
—
0
1
0
0
CLR (opr)
0
M
6
6
7
18
CENTRAL PROCESSING UNIT
TECHNICAL DATA
3-9
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