Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM Registers
10.6 CGM Registers
Three registers control and monitor operation of the CGM:
1. PLL control register (PCTL)
2. PLL bandwidth control register (PBWC)
3. PLL programming register (PPG)
10.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, and the base clock selector bit.
Address: $001C
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
1
2
1
1
1
Bit 0
1
Read:
Write:
Reset:
PLLF
0
1
1
1
1
= Unimplemented
Figure 10-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate a CPU interrupt
request when the LOCK bit toggles, setting the PLL flag, PLLF. When
the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates a CPU interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
MC68HC908AS60 — Rev. 1.0
Technical Data
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
