Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM Registers
10.6.3 PLL Programming Register
The PLL programming register (PPG) contains the programming
information for the modulo feedback divider and the programming
information for the hardware configuration of the VCO.
Address: $001E
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
1
4
MUL4
0
3
VRS7
0
2
VRS6
1
1
VRS5
1
Bit 0
VRS4
0
Read:
Write:
Reset:
Figure 10-6. PLL Programming Register (PPG)
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See 10.4.2.1 Circuits and
10.4.2.4 Programming the PLL.) A value of $0 in the multiplier select
bits configures the modulo feedback divider the same as a value
of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
Table 10-2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
0001
0010
0011
1
1
2
3
1101
1110
1111
13
14
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
MC68HC908AS60 — Rev. 1.0
Technical Data
Clock Generator Module (CGM)
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