Freescale Semiconductor, Inc.
Computer Operating Properly (COP) Module
14.3 Functional Description
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 8,176 or 262,128 CGMXCLK
cycles, depending on the state of the COP long timeout bit, COPL, in the
CONFIG-1.
COP timeout period = 8,176 or 22,128 / fOSC
When COPL = 1, a 4.9152-MHz crystal gives a COP timeout period of
53.3 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 4–12 of
the SIM counter.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held
at VHI. During the break state, VHI on the RST pin disables the COP.
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
Technical Data
MC68HC908AS60 — Rev. 1.0
Computer Operating Properly (COP) Module
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