Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI) Module
15.3 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of VDD pin level
15.4 Functional Description
Figure 15-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor VDD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when VDD falls below a voltage, LVITRIPF, and remains at or
below that level for nine or more consecutive CPU cycles. LVISTOP
enables the LVI module during stop mode. This will ensure when the
STOP instruction is implemented, and the LVI will continue to monitor
the voltage level on VDD. LVIPWR, LVISTOP, and LVIRST are in the
configuration register (CONFIG-1). See Section 11. Configuration
Register (CONFIG-1).
VDD
LVIPWR
FROM CONFIG-1
FROM CONFIG-1
CPU CLOCK
LVIRST
LVI
RESET
VDD
DIGITAL FILTER
V
DD > LVITRIP = 0
LOW V
DD
DETECTOR
VDD < LVITRIP = 1
STOP MODE
FILTER
BYPASS
ANLGTRIP
LVIOUT
LVISTOP
FROM CONFIG-1
Figure 15-1. LVI Module Block Diagram
Technical Data
MC68HC908AS60 — Rev. 1.0
Low-Voltage Inhibit (LVI) Module
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