System Integration Module (SIM)
9.8.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop mode or wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
Note: Writing a logic 0 clears SBSW.
R
= Reserved
Figure 9-20. SIM Break Status Register (SBSR)
SBSW — Break Wait Bit
This status bit is set when a break interrupt causes an exit from wait
mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting 1 from it. The
following code is an example.
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the break
service routine software.
HIBYTE
LOBYTE
EQU
EQU
If not SBSW, do RTI
BRCLR
SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN
PULH
RTI
Technical Data
152
MC68HC908LJ12 — Rev. 2.1
System Integration Module (SIM)
Freescale Semiconductor
FREESCALE [ Freescale ]
