Memory Map
Addr.
Register Name
Bit 7
PTA7
U
6
PTA6
U
5
PTA5
U
4
PTA4
U
3
PTA3
U
2
PTA2
U
1
PTA1
U
Bit 0
PTA0
U
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Port A Data Register
(PTA)
$0000
PTB7
U
PTB6
U
PTB5
U
PTB4
U
PTB3
U
PTB2
U
PTB1
U
PTB0
U
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
PTC7
U
PTC6
U
PTC5
U
PTC4
U
PTC3
U
PTC2
U
PTC1
U
PTC0
U
Port C Data Register
(PTC)
PTD7
U
PTD6
U
PTD5
U
PTD4
U
PTD3
U
PTD2
U
PTD1
U
PTD0
U
Port D Data Register
(PTD)
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
0
DDRA0
0
Data Direction Register A
(DDRA)
DDRB7
0
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
DDRB2
0
DDRB1
0
DDRB0
0
Data Direction Register B
(DDRB)
DDRC7
0
DDRC6
0
DDRC5
0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
Data Direction Register C
(DDRC)
DDRD7
0
DDRD6
0
DDRD5
0
DDRD4
0
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12)
Technical Data
46
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Memory Map
FREESCALE [ Freescale ]
