Freescale Semiconductor, Inc.
Table 9-1 Timer Summary
XTAL Frequencies
4.0 MHz
1.0 MHz
1000 ns
8.0 MHz
2.0 MHz
500 ns
12.0 MHz
3.0 MHz
16.0 MHz
4.0 MHz
250 ns
Other Rates
(E)
Control Bits
333 ns
(1/E)
PR1, PR0
Main Timer Count Rates
0 0
1 count —
overflow —
1.0 µs
65.536 ms
500 ns
32.768 ms
333 ns
21.845 ms
250 ns
16.384 ms
(1/E)
(2 /E)
16
0 1
1 count —
overflow —
4.0 µs
262.14 ms
2.0 µs
131.07 ms
1.333 µs
87.381 ms
1.0 µs
65.536 ms
(4/E)
(2 /E)
18
1 0
1 count —
overflow —
8.0 µs
524.29 ms
4.0 µs
262.14 ms
2.667 µs
174.76 ms
2.0 µs
131.07 ms
(8/E)
(2 /E)
19
1 1
1 count —
overflow —
16.0 µs
1.049 s
8.0 µs
524.29 ms
5.333 µs
349.52 ms
4.0 µs
262.14 ms
(16/E)
(2 /E)
20
9.1 Timer Structure
Figure 9-2 shows the capture/compare system block diagram. The port A pin control
block includes logic for timer functions and for general-purpose I/O. For pins PA3,
PA2, PA1, and PA0, this block contains both the edge-detection logic and the control
logic that enables the selection of which edge triggers an input capture. The digital lev-
el on PA[3:0] can be read at any time (read PORTA register), even if the pin is being
used for the input capture function. Pins PA[6:3] are used for either general-purpose
I/O, or as output compare pins. When one of these pins is being used for an output
compare function, it cannot be written directly as if it were a general-purpose output.
Each of the output compare functions (OC[5:2]) is related to one of the port A output
pins. Output compare one (OC1) has extra control logic, allowing it optional control of
any combination of the PA[7:3] pins. The PA7 pin can be used as a general-purpose
I/O pin, as an input to the pulse accumulator, or as an OC1 output pin.
TIMING SYSTEM
TECHNICAL DATA
9-3
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