Freescale Semiconductor, Inc.
9.2.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit free-running counter
value is transferred into the input capture register pair as a single 16-bit parallel trans-
fer. Timer counter value captures and timer counter incrementing occur on opposite
half-cycles of the phase 2 clock so that the count value is stable whenever a capture
occurs. The TICx registers are not affected by reset. Input capture values can be read
from a pair of 8-bit read-only registers. A read of the high-order byte of an input capture
register pair inhibits a new capture transfer for one bus cycle. If a double-byte read in-
struction, such as LDD, is used to read the captured value, coherency is assured.
When a new input capture occurs immediately after a high-order byte read, transfer is
delayed for an additional cycle but the value is not lost.
TIC1–TIC3 — Timer Input Capture
$1010–$1015
$1010
$1011
$1012
$1013
$1014
$1015
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
TIC1 (High)
TIC1 (Low)
TIC2 (High)
TIC2 (Low)
TIC3 (High)
TIC3 (Low)
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
TICx not affected by reset.
9.2.3 Timer Input Capture 4/Output Compare 5 Register
Use TI4/O5 as either an input capture register or an output compare register, depend-
ing on the function chosen for the PA3 pin. To enable it as an input capture pin, set the
I4/O5 bit in the pulse accumulator control register (PACTL) to logic level one. To use
it as an output compare register, set the I4/O5 bit to a logic level zero. Refer to 9.6
Pulse Accumulator.
TI4/O5 — Timer Input Capture 4/Output Compare 5
$101E, $101F
$101E
$101F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TI4/O5 (High)
TI4/O5 (Low)
The TI4/O5 register pair resets to ones ($FFFF).
9.3 Output Compare
Use the output compare (OC) function to program an action to occur at a specific time
— when the 16-bit counter reaches a specified value. For each of the five output com-
pare functions, there is a separate 16-bit compare register and a dedicated 16-bit com-
parator. The value in the compare register is compared to the value of the free-running
counter on every bus cycle. When the compare register matches the counter value, an
output compare status flag is set. The flag can be used to initiate the automatic actions
for that output compare function.
TIMING SYSTEM
MC68HC11F1
9-6
TECHNICAL DATA
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