Freescale Semiconductor, Inc.
TOC1–TOC4 — Timer Output Compare
$1016–$101D
$1016
$1017
$1018
$1019
$101A
$101B
$101C
$101D
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
TOC1 (High)
TOC1 (Low)
TOC2 (High)
TOC2 (Low)
TOC3 (High)
TOC3 (Low)
TOC4 (High)
TOC4 (Low)
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
All TOCx register pairs reset to ones ($FFFF).
9.3.2 Timer Compare Force Register
The CFORC register allows forced early compares. FOC[1:5] correspond to the five
output compares. These bits are set for each output compare that is to be forced. The
action taken as a result of a forced compare is the same as if there were a match be-
tween the OCx register and the free-running counter, except that the corresponding
interrupt status flag bits are not set. The forced channels trigger their programmed pin
actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is pro-
grammed to toggle its output on a successful compare because a normal compare that
occurs immediately before or after the force can result in an undesirable operation.
CFORC — Timer Compare Force
$100B
Bit 7
FOC1
0
6
FOC2
0
5
FOC3
0
4
FOC4
0
3
FOC5
0
2
—
0
1
—
0
Bit 0
—
RESET:
0
FOC[1:5] — Force Output Comparison
When the FOC bit associated with an output compare circuit is set, the output compare
circuit immediately performs the action it is programmed to do when an output match
occurs.
0 = Not affected
1 = Output x action occurs
Bits [2:0] — Not implemented
Always read zero
9.3.3 Output Compare Mask Registers
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1
compare. The bits of the OC1M register correspond to PA[7:3].
TIMING SYSTEM
MC68HC11F1
9-8
TECHNICAL DATA
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