Freescale Semiconductor, Inc.
Table 4-1 Register and Control Bit Assignments (Continued)
The register block can be remapped to any 4-Kbyte boundary.
Bit 7
SPIE
SPIF
Bit 7
TCLR
R8
6
5
4
MSTR
MODF
4
3
2
1
Bit 0
SPR0
Bit 0
$1028
$1029
$102A
$102B
$102C
$102D
$102E
$102F
$1030
$1031
$1032
$1033
$1034
$1035
$1036
$1037
$1038
$1039
$103A
$103B
$103C
$103D
$103E
$103F
$1040
to
SPE
DWOM
CPOL
CPHA
SPR1
SPCR
SPSR
SPDR
WCOL
0
0
0
0
6
0
5
3
2
1
Bit 0
SCP1
SCP0
M
RCKB
SCR2
SCR1
SCR0 BAUD
T8
TCIE
TC
6
0
WAKE
0
0
0
SCCR1
SCCR2
SCSR
SCDR
ADCTL
ADR1
ADR2
ADR3
ADR4
TIE
RIE
ILIE
IDLE
4
TE
RE
RWU
SBK
0
TDRE
Bit 7
CCF
Bit 7
Bit 7
Bit 7
Bit 7
0
RDRF
OR
NF
FE
5
3
2
1
Bit 0
CA
0
SCAN
MULT
4
CD
CC
CB
6
5
5
5
5
0
3
2
1
Bit 0
Bit 0
Bit 0
Bit 0
6
4
3
2
1
6
4
3
3
2
2
1
1
6
4
0
PTCON
BPRT3
BPRT2
BPRT1
BPRT0 BPROT
Reserved
Reserved
GWOM
ADPU
Bit 7
CWOM
CSEL
6
CLK4X
IRQE
5
0
0
CME
3
0
0
0
OPT2
DLY
4
FCME
2
CR1
1
CR0
Bit 0
OPTION
COPRST
ODD
EVEN
SMOD
RAM2
0
0
BYTE
IRV
ROW
PSEL3
REG3
DISR
1
ERASE
PSEL2
REG2
FCM
EELAT
PSEL1
REG1
FCOP
1
EEPGM PPROG
PSEL0 HPRIO
REG0 INIT
RBOOT
RAM3
TILOP
EE3`
MDA
RAM1
OCCR
EE1
RAM0
CBYP
EE0
0
TEST1
EE2
NOCOP
EEON CONFIG
Reserved
$105B
$105C
$105D
$105E
$105F
Reserved
PSTHB CSSTRH
PSIZB CSCTL
IO1SA
IO1EN
GA15
IO1SB
IO1PL
GA14
IO2SA
IO2EN
GA13
0
IO2SB
IO2PL
GA12
GSTHA
GCSPR
GA11
GSTHB
PCSEN
GA10
PSTHA
PSIZA
0
0
CSGADR
IO1AV
IO2AV
GNPOL
GAVLD
GSIZA
GSIZB
GSIZC CSGSIZ
4.3 System Initialization
Registers and bits that control initialization and the basic operation of the MCU are pro-
tected against writes except under special circumstances. The following table lists reg-
isters that can be written only once after reset or that must be written within the first 64
cycles after reset.
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11F1
4-6
TECHNICAL DATA
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