BASIC CONNECTIONS
Pin Descriptions
Top View
X
OUT
Y
OUT
Z
OUT
N/C
POWER SUPPLY
PCB Layout
16 15
g-Select1
g-Select2
V
DD
V
SS
1
2
3
4
5
N/C
6
N/C
14 13
12
11
10
9
7
N/C
8
N/C
Sleep Mode
N/C
Accelerometer
N/C
N/C
V
DD
V
SS
Sleep Mode
g-Select1
g-Select2
X
OUT
Y
OUT
Z
OUT
Description
R
C
R
C
R
C
C
C
V
RH
P0
P1
P2
A/D
IN
A/D
IN
A/D
IN
Microcontroller
V
DD
V
SS
C
Figure 4. Pinout Description
Table 4. Pin Descriptions
Pin No.
1
2
3
4
5-7
8 - 11
12
13
14
15
16
Pin Name
g-Select1
g-Select2
V
DD
V
SS
N/C
N/C
Sleep Mode
Z
OUT
Y
OUT
X
OUT
N/C
Logic input pin to select g level.
Logic input pin to select g level.
Power Supply Input
Power Supply Ground
No internal connection.
Leave unconnected.
Unused for factory trim.
Leave unconnected.
Logic input pin to enable product or
Sleep Mode.
Z direction output voltage.
Y direction output voltage.
X direction output voltage.
No internal connection.
Leave unconnected.
Figure 6. Recommended PCB Layout for Interfacing
Accelerometer to Microcontroller
NOTES:
1. Verify V
DD
line has the ability to reach 2.2 V in < 0.1
ms as measured on the device at the V
DD
pin. Rise
times greater than this most likely will prevent start up
operation.
2. Physical coupling distance of the accelerometer to
the microcontroller should be minimal.
3. The flag underneath the package is internally
connected to ground. It is not recommended for the
flag to be soldered down.
4. Place a ground plane beneath the accelerometer to
reduce noise, the ground plane should be attached to
all of the open ended terminals shown in
5. Use an RC filter with 1.0 kΩ and 0.1 µF on the
outputs of the accelerometer to minimize clock noise
(from the switched capacitor filter circuit).
6. PCB layout of power and ground should not couple
power supply noise.
7. Accelerometer and microcontroller should not be a
high current path.
8. A/D sampling rate and any external power supply
switching frequency should be selected such that
they do not interfere with the internal accelerometer
sampling frequency (11 kHz for the sampling
frequency). This will prevent aliasing errors.
9. PCB layout should not run traces or vias under the
QFN part. This could lead to ground shorting to the
accelerometer flag.
Logic
Inputs
1
g-Select1
Z
OUT
13
1 kΩ
0.1
μF
V
DD
2 g-Select2
MMA7260QT
3
V
DD
Y
OUT
14
1 kΩ
0.1
μF
0.1
μF
4
12
Logic
Input
V
SS
Sleep Mode
X
OUT
15
1 kΩ
0.1
μF
Figure 5. Accelerometer with Recommended
Connection Diagram
MMA7260QT
Sensors
Freescale Semiconductor
5
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
