Electrical Characteristics
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
RSTCFG
WKPCFG
4
Figure 4. Reset and Configuration Pin Timing
3.13.2
Num
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
IEEE 1149.1 Interface Timing
Table 20. JTAG Pin AC Electrical Characteristics
1
Characteristic
Symbol
t
JCYC
t
JDC
t
TCKRISE
t
TMSS,
t
TDIS
t
TMSH,
t
TDIH
t
TDOV
t
TDOI
t
TDOHZ
t
JCMPPW
t
JCMPS
t
BSDV
t
BSDVZ
t
BSDHZ
t
BSDST
t
BSDHT
Min
100
40
—
5
25
—
0
—
100
40
—
—
—
50
50
Max
—
60
3
—
—
20
—
20
—
—
50
50
50
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK Cycle Time
TCK Clock Pulse Width (Measured at VDDE/2)
TCK Rise and Fall Times (40% – 70%)
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
TCK Low to TDO Data Valid
TCK Low to TDO Data Invalid
TCK Low to TDO High Impedance
JCOMP Assertion Time
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
TCK Falling Edge to Output Valid out of High Impedance
TCK Falling Edge to Output High Impedance
Boundary Scan Input Valid to TCK Rising Edge
TCK Rising Edge to Boundary Scan Input Invalid
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V,
VDD33 and VDDSYN = 3.0V to 3.6V, T
A
= TL to TH, and CL = 30pF with DSC = 0b10, SRC = 0b11. See
for functional
specifications.
MPC5554 Microcontroller Data Sheet, Rev. 1.4
26
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
