Electrical Characteristics
Table 14. Flash Program and Erase Specifications
1
(continued)
Num
10
8
11
1
2
3
4
5
6
Characteristic
64 Kbyte Block Pre-program and Erase Time
128 Kbyte Block Pre-program and Erase Time
Minimum operating frequency for program and erase
operations
6
Symbol
T
64kpperase
T
128kpperase
—
Min
—
—
25
Typ
400
500
—
Initial
Max
2
500
1250
—
Max
3
5000
15,000
—
Unit
ms
ms
MHz
Typical program and erase times assume nominal supply values and operation at 25
o
C.
Initial factory condition:
≤
100 program/erase cycles, 25
o
C, typical supply voltage, 80MHz minimum system frequency.
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
Actual hardware programming times. This does not include software overhead.
Page size is 256 bits (8 words).
Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency
condition.
Table 15. Flash EEPROM Module Life (Full Temperature Range)
Num
1a
1b
2
Characteristic
Number of Program/Erase cycles per block for 16 Kbyte, 48 Kbyte, and 64
Kbyte blocks over the operating temperature range (T
J
)
Number of Program/Erase cycles per block for 128 Kbyte blocks over the
operating temperature range (T
J
)
Data retention
Blocks with 0 – 1,000 P/E cycles
Blocks with 1,001 – 100,000 P/E cycles
Symbol
P/E
P/E
Retention
20
5
Min
100,000
10,000
Typical
1
—
Unit
cycles
100,000 cycles
—
years
1
Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 “Typical Endurance
for Nonvolatile Memory.”
shows the FLASH_BIU settings versus frequency of operation. Refer to the device Reference
Manual for definitions of these bit-fields.
Table 16. FLASH_BIU Settings vs. Frequency of Operation
Maximum Frequency (MHz)
up to and including 82 MHz
1
APC
0b001
RWSC
0b001
WWSC
0b01
DPFEN
0b00,
0b01, or
0b11
2
0b00,
0b01, or
0b11
0b00,
0b01, or
0b11
0b00
IPFEN
0b00,
0b01, or
0b11
0b00,
0b01, or
0b11
0b00,
0b01, or
0b11
0b00
PFLIM
0b000-
0b110
3
0b000-
0b110
0b000-
0b110
0b000
BFEN
0b0, 0b1
4
up to and including 102 MHz
5
0b001
0b010
0b01
0b0, 0b1
up to and including132 MHz
6
0b010
0b011
0b01
0b0, 0b1
Default Setting after Reset
1
0b111
0b111
0b11
0b0
This setting allows for 80 MHz system clock with 2% frequency modulation.
MPC5554 Microcontroller Data Sheet, Rev. 1.4
22
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
