FEC Electrical Characteristics
shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 74. MII Async Inputs Timing Diagram
15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
provides information on the MII serial management channel signal timing. The FEC functions correctly
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 37. MII Serial Management Channel Timing
Num
M10
M11
M12
M13
M14
M15
Characteristic
MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
MII_MDIO (input) to MII_MDC rising edge setup
MII_MDIO (input) to MII_MDC rising edge hold
MII_MDC pulse width high
MII_MDC pulse width low
Min
0
—
10
0
40%
40%
Max
—
25
—
—
60%
60%
Unit
ns
ns
ns
ns
MII_MDC period
MII_MDC period
shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
M10
MII_MDIO (output)
M11
MII_MDIO (input)
M12
M13
Figure 75. MII Serial Management Channel Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
74
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
