Electrical Characteristics
data from the JTAG logic. Shifting out of data depends on the state of the JTAG controller state machine
and the instruction currently in the instruction register. This data shift occurs on the falling edge of TCK.
When TDO is not outputting test data, it is three-stated. TDO can also be placed in three-state mode to
allow bussed or parallel connections to other devices having JTAG. This signal also provides single-bit
communication for the debug module responses.
8.21 Clock and Reset Signals
These signals configure the SCF5249 and provide interface signals to the external system.
8.21.1 Reset In
Asserting RSTI causes the SCF5249 to enter reset exception processing. When RSTI is recognized, the
data bus is tri-stated.
8.21.2 System Bus Input
The CRIN signal is the system clock input. The device has no on-chip clock oscillator, and needs an
external oscillator.
9
Electrical Characteristics
Table 15. Maximum Ratings
Rating
Supply Core Voltage
Maximum Core Operating Voltage
Minimum Core Operating Voltage
Supply I/O Voltage
Maximum I/O Operating Voltage
Minimum I/O Operating Voltage
Input Voltage
Storage Temperature Range
Symbol
V
cc
V
cc
V
cc
V
cc
V
cc
V
cc
V
in
T
stg
Value
-0.5 to +2.5
+1.98
+1.62
-0.5 to +4.6
+3.6
+3.0
-0.5 to +6.0
-65 to150
Units
V
V
V
V
V
V
V
o
C
Table 16. Operating Temperature
Characteristic
Maximum Operating Ambient Temperature
Minimum Operating Ambient Temperature
Note:
Symbol
T
Amax
T
Amin
Value
85
1
0
Units
ο
C
o
C
This published maximum operating ambient temperature should be used only as a system design guideline. All device
operating parameters are guaranteed only when the junction temperature does not exceed 105
°
C.
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
28
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
