Electrical Characteristics
9.1
Supply Voltage Sequencing and Separation Cautions
shows two situations to avoid in sequencing the CoreVdd and PADVdd (I/O) and PLLL supplies.
Figure 2. Supply Voltage Sequencing and Separation Cautions
CoreVdd supply should not be allowed to rise early (1). This is usually avoided by running the regulator
for the CoreVdd supply (1.8 V) from the voltage generated by the 3.3V supply (PADVdd). This keeps the
CoreVdd supply from rising faster than PADVdd supply.
Also CoreVdd, PLLGVdd, PLLCVdd supply should not rise so late that a large voltage difference is
allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes
in series between supplies. The series diodes forward bias when the difference between PADVdd and
CoreVdd reaches approximately 2.1V, causing CoreVdd to rise as PADVdd ramps up. When the CoreVdd
regulator begins proper operation, the difference between supplies should not exceed 1.5 V and conduction
through the diode chain reduces to essentially leakage current.
During supply sequencing, the following general relationship should be adhered to: PADVdd, >=
CoreVdd, PLLGVdd, >= (PADVdd - 2.1 V).
The PLL core supplies (PLLGVdd and PLLCVdd) should comply with these constraints just as the
CoreVdd does. In practice, PLLGVdd and PLLCVdd are typically connected directly to the CoreVdd with
some filtering. Further, the PLL PAD supply (PLL1VDD) would be connected directly to the PAD supply
via some filtering.
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
30
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
