Electrical Characteristics
CRIN
PSTCLK
BCLK
C6
C6
C7
C8
C8
Figure 5. Clock Timing Definition
NOTE
Signals above are shown in relation to the clock. No relationship between
signals is implied or intended.
9.1.1 Processor Bus Input Timing Specification
Table 20 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the SCLK output. All other timing relationships can be
derived from these values.
Table 20. External Bus Input Timing Specifications
Num
Characteristica
Units
Symbol Min
Max
B0
B1
B2
B4
SCLK
tCYC
tCVCH
tCHCII
tDIVCH
14.26
—
—
—
—
ns
ns
ns
ns
Control input valid to SCLK highb
SCLK high to control inputs validb
Data input (D[31:0]) valid to SCLK high
10
2
6
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
33
FREESCALE [ Freescale ]
