Electrical Characteristics
Table 26. I2C-Bus Input Timing Specifications Between SCL and SDA
Num
Characteristic
Stop Condition Setup Time
Units
Min
Max
M9
tbd
—
bus clocks
Table 27. I2C-Bus Output Timing Specifications Between SCL and SDA
Num
Characteristic
Units
Min
Max
M11
M21
M32
Start Condition Hold Time
tbd
tbd
—
—
—
bus clocks
bus clocks
mSec
Clock Low Period
SCL/SDA Rise Time
tbd
(VIL= 0.5 V to VIH = 2.4 V)
M41
M53
Data Hold Time
tbd
—
—
bus clocks
nSec
SCL/SDA Fall Time
tbd
(VIH= 2.4 V to VIL = 0.5 V)
M61
M71
M81
Clock High time
Data Setup Time
tbd
tbd
tbd
—
—
—
bus clocks
bus clocks
bus clocks
Start Condition Setup Time
(for repeated start condition only)
M91
Stop Condition Setup Time
tbd
—
bus clocks
1. Note: Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed
with the maximum frequency (MFDR = 0x20) will result in minimum output timings as shown in the above
table. The MBUS interface is designed to scale the actual data transition time to move it to the middle of
the SCL low period. The actual position is affected by the prescale and division values programmed into
the MFDR; however, numbers given in the above table are the minimum values.
2. Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the
time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up
resistor values.
3. Specified at a nominal 20 pF load.
M2
M6
M5
SCL
SDA
M3
M1
M4
M7
M8
M9
Figure 13. I2C Timing Definition
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
41
FREESCALE [ Freescale ]
