Electrical Characteristics
Table 28. I2C Output Bus Timings
Num
M10
3
M11
M12
1
M13
2
1.
Characteristic
Min
SCL, SDA Valid to SCLK (input setup)
SCLK to SCL, SDA Invalid (input hold)
SCLK to SCL, SDA Low (output valid)
SCLK to SCL, SDA Invalid (output hold)
tbd
tbd
—
tbd
Max
—
—
tbd
—
Units
nSec
nSec
nSec
nSec
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this
specification applies only when SCL or SDA are driven low by the processor. The time required for SCL or
SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this
specification applies only when SCL or SDA are actively being driven or held low by the processor.
SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular
clock is required.
2.
3.
SCLK
M10
SCL, SDA IN
M11
SCL, SDA OUT
M12
SCL, SDA OUT
M13
Figure 14. I
2
C and System Clock Timing Relationship
Table 29. General-Purpose I/O Port AC Timing Specifications
Num
Characteristic
Min
P1
P2
GPIO Valid to SCLK (input setup)
SCLK to GPIO Invalid (input hold)
tbd
tbd
Max
—
—
nSec
nSec
Units
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
42
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
