FT2232L Dual USB UART / FIFO I.C.
3.0
Simplified Block Diagram
PWREN#
48MHz
Baud Rate
Generator
Channel A
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
VCC
PWRCTL
Dual Port TX
Buffer
128 bytes
3V3OUT
3.3 Volt
LDO
Regulator
Dual Port RX
Buffer
384 Bytes
Multi-
Purpose
UART / FIFO
Controller
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
USBDP
USB
Transceiver
USBDM
Serial Interface
Engine
( SIE )
USB
Protocol Engine
SI/WUA
Channel B
Dual Port TX
Buffer
128 bytes
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
USB DPLL
Dual Port RX
Buffer
384 Bytes
Multi-
Purpose
UART / FIFO
Controller
XTOUT
6MHZ
Oscillator
x8 Clock
Multiplier
48MHz
48MHz
12MHz
Baud Rate
Generator
BCBUS3
SI/WUB
XTIN
3V3OUT
EECS
TEST
GND
EEPROM
Interface
EESK
EEDATA
RESET#
RESET
GENERATOR
RSTOUT#
Figure 1 - FT2232L Simplified Block Diagram
3.1
•
Functional Block Descriptions
3.3V LDO Regulator
The 3.3V LDO Regulator generates the 3.3 volt
reference voltage for driving the USB transceiver
cell output buffers. It requires an external
decoupling capacitor to be attached to the 3V3OUT
regulator output pin. It also provides 3.3V power to
the RSTOUT# pin. The main function of this block
is to power the USB Transceiver and the Reset
Generator Cells rather than to power external logic.
However, external circuitry requiring 3.3V nominal
at a current of not greater than 5mA could also
draw its power from the 3V3OUT pin if required.
•
USB Transceiver
The USB Transceiver Cell provides the USB 1.1 /
USB 2.0 full-speed physical interface to the USB
cable. The output drivers provide 3.3 volt level slew
rate control signalling, whilst a differential receiver
and two single ended receivers provide USB data
in, SEO and USB Reset condition detection.
•
USB DPLL
The USB DPLL cell locks on to the incoming NRZI
USB data and provides separate recovered clock
and data signals to the SIE block.
DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 6 of 51
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