FT2232L Dual USB UART / FIFO I.C.
•
6MHz Oscillator
The 6MHz Oscillator cell generates a 6MHz
reference clock input to the x8 Clock multiplier from
an external 6MHz crystal or ceramic resonator.
•
x8 Clock Multiplier
The x8 Clock Multiplier takes the 6MHz input
from the Oscillator cell and generates a 48MHz
reference clock for the USB DPPL and the Baud
Rate Generator blocks.
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Serial Interface Engine (SIE)
The Serial Interface Engine (SIE) block performs
the Parallel to Serial and Serial to Parallel
conversion of the USB data. In accordance to the
USB 2.0 specification, it performs bit stuffing / un-
stuffing and CRC5 / CRC16 generation / checking
on the USB data stream.
•
USB Protocol Engine
The USB Protocol Engine manages the data
stream from the device USB control endpoint. It
handles the low level USB protocol (Chapter 9)
requests generated by the USB host controller
and the commands for controlling the functional
parameters of the UART / FIFO controller blocks.
Dual Port TX Buffers (128 bytes)
Data from the USB data out endpoint is stored
in the Dual Port TX buffer and removed from the
buffer to the transmit register under control of the
UART FIFO controller.
•
Dual Port RX Buffers (384 bytes)
Data from the UART / FIFO controller receive
register is stored in the Dual Port RX buffer prior
to being removed by the SIE on a USB request for
data from the device data in endpoint.
Multi-Purpose UART / FIFO Controllers
The Multi-purpose UART / FIFO controllers handle
the transfer of data between the Dual Port RX
and TX buffers and the UART / FIFO transmit
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Baud Rate Generator
The Baud Rate Generator provides a x16 clock
input to the UART’s from the 48MHz reference
clock and consists of a 14 bit prescaler and 3
register bits which provide fine tuning of the baud
rate (used to divide by a number plus a fraction).
This determines the Baud Rate of the UART which
is programmable from 183 baud to 3 million baud.
•
RESET Generator
The Reset Generator Cell provides a reliable
power-on reset to the device internal circuitry
on power up. An additional RESET# input and
RSTOUT# output are provided to allow other
devices to reset the FT2232L, or the FT2232L
to reset other devices respectively. During reset,
RSTOUT# is driven low, otherwise it drives out
at the 3.3V provided by the onboard regulator.
RSTOUT# can be used to control the 1.5K
pull-up on USBDP directly where delayed USB
enumeration is required. It can also be used to
reset other devices. RSTOUT# will stay high-
impedance for approximately 5ms after VCC
has risen above 3.5V AND the device oscillator is
running AND RESET# is high. RESET# should
be tied to VCC unless it is a requirement to reset
the device from external logic or an external reset
generator I.C.
and receive registers. When configured as a
UART it performs asynchronous 7 / 8 bit Parallel
to Serial and Serial to Parallel conversion of the
data on the RS232 (RS422 and RS485) interface.
Control signals supported by UART mode include
RTS, CTS, DSR , DTR, DCD and RI. There
are also transmitter enable control signal pins
(TXDEN) provided to assist with interfacing to
RS485 transceivers. RTS/CTS, DSR/DTR and
Xon/Xoff handshaking options are also supported.
Handshaking, where required, is handled in
hardware to ensure fast response times. The
UART’s also supports the RS232 BREAK setting
and detection conditions.
•
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DS2232L Version 1.4
© Future Technology Devices International Ltd. 2005 Page 7 of 51
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