3.3 AC Switching Characteristics
The FT8U100AX operates off of a 48MHz input frequecy. This is divided by 4 and passed to the chip’s on board
microcontroller, FTDI’s EMCU, as a 12MHz input clock. The user does not have visibility of this clock however it is
useful to relate timings to this clock and as such it is inlcuded.
The key timings for the FT8U100AX relate to ROM access and reset operations.
ROM access wait states can be set from 0 to 3 wait states under the control of the Chip Control Register at address
CCh.
CLK12
ROMA
TRAH
ROMD
TRDS
TACC
Program ROM data read (zero wait state)
Symbol
TRAH
Parameter
Address valid from
CLK rising
ROM data setup to
CLK
ROM access time
Conditions
VCC3 = 3.0 to 3.6V
Min
Typ
Max
25
Units
nS
TRDS
VCC3 = 3.0 to 3.6V
10
nS
TACC
VCC3 = 3.0 to 3.6V
55
nS
The above table shows the case for a zero wait state program ROM read - where the read must take place within 80nS.
This requires a ROM access time of 55nS. For One wait state operation 125nS parts can be used.
Future Technology Devices Intl.
FT8U100AX Product Data Rev 0.90
Page
10
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