4. Internal IO Register Summary
The registers contained within the FT8U100AX can be described in terms of the following five main groups
USB Downstream Registers
USB Suspend Registers
USB Upstream Registers
USB Device/EndPoint Registers
Chip Control Registers
A summary of the function of each register group is given followed by tables detailing the register contents. Where
necessary a short description of the function of specific registers is provided.
4.1 USB Downstream Registers
The following registers provide indexing, control and status information for up to seven USB downstream ports
supported by the FT8U100AX.
This register acts as an index into the downstream port data registers - which provide control and status for even and
odd indexes respectively.
USB Hub Downstream Port index register
Address = 90h w/o
0/1 – Select Port 1
2/3 – Select Port 2
4/5 – Select Port 3
6/7 – Select Port 4
8/9 – Select Port 5
A/B – Select Port 6
C/D – Select Port 7
USB Hub Downstream Port Data register
Address = 91h r/w
Even index – control
Bit 0 – Set Power On
Bit 1 – Set Port Enable
Bit 2 – Set Port Reset
Bit 3 – Set Port Suspend
Bit 4 – Set Power OK
Bit 5 – Set Reset Activity Detect
Bit 6 – Set Signal Resume
Bit 7 – Set SE0 (set single ended zero)
odd index – status
Bit 0 - Connect Detected
Bit 1 - Port Enabled
Bit 2 - Port Suspended
Bit 3 - Port Over Current detected
Bit 4 - Port Reset
Bit 5 - Enable Power Interrupt
Bit 6 - NOT Full Speed Device
Bit 7 - Resume Signalled
USB Hub Downstream Port Control register
Address = 92h r/w
Bit 0 - Frame timer enable
Bit 1 - Hub Suspend
Bit 2 - Signal Resume
Bit 3 - Three bit window for seeing SOF
Bit 4 - IRQMask masks Host resume IRQ
Bit 5 - Force EOF2 – End of Frame2 set 10 clocks before the start of frame
Future Technology Devices Intl.
FT8U100AX Product Data Rev 0.90
Page 14
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
