MB15C03
Figure 4 The flow of serial data
14-bit binary programmable reference counter
Programmable
reference divider
14
AND
14-bit latch
14
Data
C*
Clock
LE
AND
18
18-bit shift register
18-bit latch
6
Prescaler
12
Programmable
divider
6-bit binary swallow counter 12-bit binary programmable
counter
* : Control register
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table.2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of
Table.2.2 represent the divide ratio of programmable counter. The control bit is set to 0.
Table. 2 Divide ratio for the programmable divider
Table.2.1 Swallow counter divider A
Divide
ratio
(A)
0
1
•
63
A
0
0
1
•
1
A
1
0
0
•
1
A
2
0
0
•
1
A
3
0
0
•
1
A
4
0
0
•
1
A
5
0
0
•
1
Divide
ratio
(N)
5
6
•
4095
Table.2.2 Programmable counter divider N
N
0
1
0
•
1
N
1
0
1
•
1
N
2
1
1
•
1
N
3
0
0
•
1
N
4
0
0
•
1
N
5
0
0
•
1
N
6
0
0
•
1
N
7
0
0
•
1
N
8
0
0
•
1
N
9
0
0
•
1
N
10
0
0
•
1
N
11
0
0
•
1
Note: Less than 5 is prohibited.
12
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