MB15C03
(2) Programmable divider
The f
vco
input through fin pin is divided by the programmable divider and then output to the phase comparator
as f
p
. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable
counter, and a controller which controls the divide ratio of the prescaler.
Divide ratio range:
Prescaler : M = 64, M + 1 = 65
Swallow counter : A = 0 to 63
Programmable counter : N = 5 to 4095
The MB15C03 uses the pulse swallow method; consequently, the divide rations of the swallow and programmable
counters must satisfy the relationship N > A.
The total divide ratio of the programmable divider is calculated as follows:
Total divide ratio = (M+1) x A + M x (N-A) = M x N + A = 64 x N + A
When N is set within 5<N<63, the possible divide ratio A of the swallow counter can take values 0<A<N-1
because N must be greater than A. For example, 0<A<19 is allowed when N = 20 but 20<A<63 is not allowed
in that case. Consequently, N>64 must be satisfied for the total divider to be set within 0<A<63.
The f
p
and fin have the following relation:
f
p
= fin / (64 x N + A)
(3) Programmable reference divider
The programmable reference divider divides the reference oscillation frequency (f
osc)
from the crystal oscillator
connected between OSC
IN
and OSC
OUT
pins or from the external oscillator input taken in directly through OSC
IN
,
pin and then, sends the resultant f
r
to the phase comparator. It consists of a 14-bit binary programmable reference
counter. When the output from the external oscillator is to be input directly to OSC
IN
pin, the connection must
be AC coupled and OSC
OUT
pin is left open. Also, to prevent OSC
OUT
from malfunctioning, its traces on the
printed circuit board must be kept minimal or eliminated entirely; whenever possible, it must be free of any form
of load.
The following divider is used:
Programmable reference counter : R = 5 to 16383
The f
r
and f
osc
have the following relation:
f
r
= f
osc
/ R
(4) Phase comparator
The phase comparator detects the phase difference between the outputs f
r
and f
p
from the dividers and generates
an error signal that is proportional to phase difference. The outputs from the phase comparator include D
O
which
takes on one of the three states, namely, “L” (low), “H” (high), and “Z” (high impedance), and is sent to the LPF
LD which indicates the PLL lock or unlock states.
(a) Phase comparator
The phase comparator detects the phase error between f
r
and f
p
, then generates an error signal that is
proportional to the phase error. The roles of the f
r
and f
p
supplied to the phase comparator may be reversed
by switching the logical input level of pin FC. This inverts the logical level of the D
O
output. The logical level
of D
O
output may be selected according to the characteristics of the external LPF and the VCO. (Refer to
Table 1.)
8
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
