MB15F72SP 参数 Datasheet PDF下载

MB15F72SP

s

FUNCTIONAL DESCRIPTION

1. Pulse swallow function :

f

VCO

= [(P

×

N) + A]

×

f

OSC

÷

R

f

VCO

: Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)

N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A : Preset divide ratio of binary 7-bit swallow counter (0

≤

A

≤

127, A < N)

f

OSC

: Reference oscillation frequency (OSC

IN

input frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2. Serial Data Input

Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sec-

tions, and programmable reference dividers of IF/RF-PLL sections are controlled individually.

Serial data of binary data is entered through Data pin.

On a rising edge of Clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable

signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data

setting.

The programmable

reference counter

for the IF-PLL

CN1

CN2

0

0

The programmable

reference counter

for the RF-PLL

1

0

The programmable

counter and the swallow

counter for the IF-PLL

0

1

The programmable

counter and the swallow

counter for the RF-PLL

1

1

(1)

Shift Register Configuration

• Programmable Reference Counter

(LSB)

Data Flow

(MSB)

1

2

3

4

5

6

7

8

9 10 11 12 13 14

15

16

17

18 19 20 21 22 23

X

X

X

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X

CS

R1 to R14

T1, T2

CN1, CN2

X

: Charge pump currnet select bit

: Divide ratio setting bits for the programmable reference counter (3 to 16,383)

: Test purpose bit

: Control bit

: Dummy bits (Set “0” or “1”)

Note : Data input with MSB first.

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