MB15F72SP
• Programmable Counter
(LSB)
Data Flow
(MSB)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
CN1 CN2 LDS
SW
IF
/
FC
IF
/
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
SW
RF
FC
RF
A1 to A7
N1 to N11
LDS
SW
IF
/SW
RF
FC
IF
/FC
RF
CN1, CN2
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: LD/fout signal select bit
: Divide ratio setting bit for the prescaler (IF : SW
IF
,RF : SW
RF
)
: Phase control bit for the phase detector (IF: FC
IF
, RF: FC
RF
)
: Control bit
Note: Data input with MSB first.
(2) Data setting
•
Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)
Divide ratio
3
4
•
•
•
16383
R14
0
0
•
•
•
1
R13
0
0
•
•
•
1
R12
0
0
•
•
•
1
R11
0
0
•
•
•
1
R10
0
0
•
•
•
1
R9
0
0
•
•
•
1
R8
0
0
•
•
•
1
R7
0
0
•
•
•
1
R6
0
0
•
•
•
1
R5
0
0
•
•
•
1
R4
0
0
•
•
•
1
R3
0
1
•
•
•
1
R2
1
0
•
•
•
1
R1
1
0
•
•
•
1
Note
:
Divide ratio less than 3 is prohibited.
•
Binary 11-bit Programmable Counter Data Setting (N1 to N11)
Divide ratio
3
4
•
•
•
2047
N11
0
0
•
•
•
1
N10
0
0
•
•
•
1
N9
0
0
•
•
•
1
N8
0
0
•
•
•
1
N7
0
0
•
•
•
1
N6
0
0
•
•
•
1
N5
0
0
•
•
•
1
N4
0
0
•
•
•
1
N3
0
1
•
•
•
1
N2
1
0
•
•
•
1
N1
1
0
•
•
•
1
Note : Divide ratio less than 3 is prohibited.
•
Binary 7-bit Swallow Counter Data Setting
(A1 to A7)
Divide ratio
0
1
•
•
•
127
A7
0
0
•
•
•
1
A6
0
0
•
•
•
1
A5
0
0
•
•
•
1
A4
0
0
•
•
•
1
A3
0
0
•
•
•
1
A2
0
0
•
•
•
1
A1
0
1
•
•
•
1
9
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
