MB86604LPFV 参数 Datasheet PDF下载

MB86604L

s

PIN DESCRIPTION

1. SCSI Interface

Pin

number

60

Symbol

REQ

Pin name

Request

I/O

I/O

Function

Transfer request signal in the information transfer phases from

target to initiator. The input signal to this pin is used for the timing

control of data transfer sequence. This is a three-state I/O pin

and an active low pin.

This pin is for the acknowledge signal from initiator to target for

the REQ signal in the information transfer phases. The input

signal to this pin is used for the timing control of data transfer

sequence. This is a three-state I/O pin and an active low pin.

This pin is for the attention signal that initiator requests target for

the message transfer phase. This is an active-low pin.

This pin is for the message signal that specifies type of

information transferred on the data bus. This is an active-low pin

and becomes “L” when message phase is specified.

This pin is for the control/data signal that specifies type of

information transferred on the data bus. This an active-low pin

and becomes “L” level when command, status, or message

phase is specified.

This pin is for the input/output signal that specifies direction of

information transferred on the data bus. This is an active-low pin.

When this pin is “L” level, the information is transferred from

target to initiator. When this pin is “H” level, the information is

transferred from initiator to target.

This pin is for the SCSI bus busy signal. In the arbitration phase,

this is for the request signal for the use of bus acquisition. This is

an active-low pin.

This pin is for the select signal used by initiator to select target

during the selection phase and by target to reselect initiator

during the reselection phase. This is an active-low pin.

This pin is for the reset signal used by any device on the bus.

When the device is an input operation, the reset signal is input to

this pin. When output operation, the reset signal is output from

this pin. This is an active-low pin.

These pins are for the bidirectional 8-bit SCSI data bus and 1-bit

odd parity line.

68

ACK

Acknowledge

I/O

71

63

ATN

MSG*

Attention

Message

I/O

I/O

61

C/D*

Control/data

I/O

58

I/O*

Input/output

I/O

69

BSY

Busy

I/O

62

SEL

Select

I/O

67

RST

Reset

I/O

11, 12, 13, DB7

17, 18, 19, to

DB0

20, 22

9

DBP

Data bus 7

to

data bus 0

Data bus

parity

I/O

* : Regarding the status of information transfer which is indicated by MSG, C/D, and I/O pins, See Table Phase Status.

4