MB86604L
(Continued)
Pin
number
100
Symbol*
BHE
(UDS)
Pin name
Bus high
enable
(strobe)
I/O
I
Function
In the 80-series mode, this pin is used for input of the bus high
enable signal (BHE) output from the MPU when the upper byte of
the data bus is valid. The BHE pin is an active-low. In the 68-
series mode, this pin functions as the upper data strobe signal
input pin (UDS) output from the MPU when the upper byte of the
data bus is valid. The UDS pin is also an active-low.
The INT and INT pins are the interrupt request signal output. The
INT pins is used for the 80-series mode (an active-high pin), and
the INT signal is used for the 68-series mode (an active-low pin).
This input pin is used to select the type of the MPU and DMA
buses. In the 80-series mode, a high level is input. In the 68-
series mode, a low level is input.
7
INT
(INT)
MODE
Interrupt
request
Mode
O
8
I
* : The pin symbols in parenthesis are the ones when the MODE input is “L”.
3. DMA Interface
Pin
number
52
Symbol*
DREQ
Pin name
DMA request
I/O
O
Function
This is an output pin of DMA transfer request signal to the DMA
controller. The data transfer between the SPC and memory via
the DMA bus is requested. This pin is an active-high.
This is a DMA acknowledge signal input pin output from the
DMA controller that enables the DMA transfer. This pin is an
active-low. When this pin is an active state, the DMA cycle (read/
write) is valid.
These pins are the input/output pins of the upper byte and parity
bit of the DMA data bus. When the signal input to the CS1 pin
(pin 80) is valid, these pins are connected directly to the MPU
data bus.
These pins are the input/output pins of the lower byte and parity
bit of the DMA data bus. When the CS1 (pin 80) input is valid,
these pins are connected directly to the MPU data bus.
51
DACK
DMA
acknowledge
I
48, 47, 46, DMD15
45, 44, 43, to
42, 41
DMD8
49
UDMDP
DMA data 15
to
DMA data 8
Upper DMA
data parity
DMA data 7
to
DMA data 0
Lower DMA
data parity
I/O read
(DMA read/
write)
I/O
39, 38, 37, DMD7
36, 35, 34, to
33, 32
DMD0
31
27
LDMDP
IORD
(DMR/W)
I/O
I
In the 80-series mode, this pin (IORD or RD) is used for the input
pin to output the data from the SPC to the DMA bus. This is an
active-low pin. In the 68-series mode, this pin functions as a
control signal input pin (DMR/W) to input/output the data to the
SPC by the DMA controller. In the output operation, this pin is on
the high-state (active-high state). In the input operation, this pin
is on the low-state (active-low state).
In the 80-series mode, this (IOWR or WR) is used for the input
pin to input the DMA bus data to the SPC. In the 68-series mode,
this pin functions as a DMA lower data strobe input (DMLDS)
that DMA controller outputs when the lower byte of the DMA bus
data is valid. Both IOWR and DMLDS pins are an active-low.
26
IOWR
(DMLDS)
I/O write
(DMA lower
data strobe)
I
(Continued)
6
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
