Preliminary
1.4. Block Description
1.5.1. PCI Block
PCI block consists of the following components :
(1) PCI Interface:
32- bit, 33MHz, PCI local bus interface compliant with PCI spec revision 2.2. This is the 5V/3.3V oper-
able local bus interface with host side.
(2) DMAC
DMA bus master which is associated with the PCI interface.
(3) Slave:
DMA slave mode controller which is used for the register access in response to the DMA bus master
request.
(4) Serial ROM Interface:
This interface connects with an EEPROM (PCI Configuration ROM) containing various information such
as PCI subsystem ID, and subsystem vendor ID.
1.5.2. OHCI Block
OHCI block includes the powerful DMA engines for ContextProgram Control, work memory, FIFO, and LINK-
Tx, - Rx sections:
(1) ContextProgramController (CPC) :
This controller is ContextProgram Processor Unit that analyzes the context programs stored in the sys-
tem memory.
For Receive state, the on- chip R- CPC transfers the OHCI packet stored in the FIFO to the system
memory via PCI interface. For Transmit state, the on- chip AT- , and IT- CPC transmit the packet stored
in the system memory to the FIFO.
This section also includes a PHY Request Unit (PRU) which works for automatically decoding the physi-
cal request packet if received.
1.5.3. ContextProgram Work Memory (CP Work)
This block is work RAM area used for storing IT- , AT- , and, Receive- context program to be processed, and
also storing header information on received physical request packet. The area is formed by 128B x 3 units of
SRAM.
1.5.4. Open HCI Registers
This block contains total 2048- byte register set as defined in the Open HCI standard. For the register map,
see Section 3 in this document.
1.5.5. FIFO
This is a 6Kbytes FIFO memory used for storing the packet received and to be transmitted. The internal area is
divided, one for Asynchronous/Isochronous Transmit (AT- FIFO and IT- FIFO) and one for Asynchronous/
Isochronous Receive (R- FIFO).
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