MB86613S 参数 Datasheet PDF下载

Preliminary

2.3. Pin Function

2.3.1. PCI Bus Interface

Notes:

I/O denotes input/output pin.

O denotes output pin.

I denotes input pin.

OD denotes open- drain output pin.

Name of pin

PCICLK

RST#

AD31 : 0

C/BE3# : 0#

PAR

FRAME#

IRDY#

TRDY#

STOP#

IDSEL

I/O

I

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

PCI bus clock input pin (Max. 33MHz)

System reset input pin.

Function

32- bit PCI Address/Data multiplexed pins.

PCI Bus Command / Byte Enable multiplexed pins.

Even Parity pin for AD31:0 and C/BE3#:0#. This pin state becomes valid after 1 PCICLK.

Frame signal pin that indicates the PCI bus is driven by the master.

Data Ready signal pin for bus master device.

Data Ready signal pin for target device.

Stop signal pin for the data transfer from target to master.

Chip select pin to access the configuration register.

Device select pin. While the device is a target, this pin outputs the select signal that indicates

the self device is selected. While the device is a master, this pin functions as an input pin to

indicate that a device on the bus is selected.

Request signal output pin to the bus arbiter to request for the PCI bus use.

Grant signal input pin from the bus arbiter to receive the response to the REQ# signal.

Data Parity Error input/output pin.

Address Parity Error output pin. (Open- drain type output pin.)

Interrupt output pin. (Open- drain type output pin.)

DEVSEL#

I/O

REQ#

GNT#

PERR#

SERR#

INTA#

O

I

I/O

OD

OD

PME#

O

PCI power management enable

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