MB90097
s
PIN DESCRIPTIONS
Pin no.
1
2
Pin name
SCLK
CS
I/O
I
I
Function
Shift clock input pin for serial transfer
This pin has an internal pull-up resistor.
Chip select pin
This pin inputs a Low level signal for serial transfer.
The pin has an internal pull-up resistor.
Serial data input pin
This pin has an internal pull-up resistor.
Reset input pin
This pin inputs a Low level signal when turning the power on.
+ 3 V power supply pin
Data input direction select pin for serial transfer
This pin inputs the Low level signal in the LSB-first transfer mode for data
input; it inputs the High level signal in the MSB-first transfer mode.
External circuit pins for display dot clock generator
Connect these pins to external “L” and “C” to form an LC oscillator circuit.
For external input of a display dot clock, input the clock signal to the EXD
pin and leave the XD pin open.
LSI test input pin
Input the Low level signal during normal use.
Ground pin
Horizontal sync signal input pin
Vertical sync signal input pin
Color code signal output pin
Display period signal output pin for output channel A
Display period signal output pin for output channel B
Display period signal output pin for output channel C
LSI test output pin
Leave this pin open (unconnected) during normal use.
3
4
5
6
SIN
RESET
V
DD
SDR
I
I
—
I
7
8
XD
EXD
O
I
9
10
20
19
18
17
16
14
15
13
11
12
TEST
GND
HSYNC
VSYNC
VC0
VC1
VC2
VC3
BLKA
BLKB
BLKC
TESTO
I
—
I
I
O
O
O
O
O
O
O
O
5
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
