MB90097
(2) Vertical and horizontal sync signal input timings
(V
DD
= 3.0 V to 3.6 V, V
GND
= 0 V, Ta = – 40°C to + 85°C)
Parameter
Horizontal sync signal rise time
Horizontal sync signal fall time
Vertical sync signal rise time
Vertical sync signal fall time
Horizontal sync signal pulse width
*1
Vertical sync signal detection setup time
*2
Vertical sync signal detection hold time
Symbol
t
HR
t
HF
t
VR
t
VF
t
WH
t
VS
t
VH
Pin name
HSYNC
VSYNC
HSYNC
VSYNC
VSYNC
Value
Min.
—
—
—
—
18
—
4
2
Max.
200
200
200
200
—
6
1H – 4
20
Unit
ns
ns
ns
ns
Dot clock
µs
Dot clock
H
*1: During the horizontal sync signal pulse period, the MB90097 stops its internal operation, disabling writing to
the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle (command 2 or
command 4 issuance cycle) to ensure that: horizontal sync signal pulse width < VRAM write cycle.
*2: Do not change the vertical sync signal (detection edge) in the vicinity of the horizontal sync signal edge of
vertical sync signal detection. Otherwise, it results in a deflection in the display when the sync signal fluctuates.
(1) VSYNC: Leading-edge operation
HSYNC: VSYNC detection at the trailing edge
t
VF
t
VS
t
VH
0.8 V
DD
0.2 V
DD
0.2 V
DD
t
VR
VSYNC
0.8 V
DD
t
HF
t
WH
t
HR
HSYNC
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Note: The above diagrams assume that sync signal input control (SIX bit) of I/O pin control (command 13-0) has
been set to negative logic (0). The H and L levels are inverted if it has been set to positive logic.
(Continued)
9
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