MB90F387S 参数 Datasheet PDF下载

MB90385 Series

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16 Mbyte CPU memory space

• 24-bit internal addressing

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Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

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Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

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Increased processing speed

• 4-byte instruction queue

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Powerful interrupt function with 8 levels and 34 factors

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Automatic data transfer function independent of CPU

• Expanded intelligent I/O service function (EI

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OS): Maximum of 16 channels

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Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)

• Clock mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode

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Process

• CMOS technology

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I/O port

• General-purpose input/output port (CMOS output) :

MB90387, MB90F387

: 34 ports (including 4 high-current output ports)

MB90387S, MB90F387S : 36 ports (including 4 high-current output ports)

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Timer

• Time-base timer, clock timer, watchdog timer: 1 channel

• 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels

• 16-bit reload timer: 2 channels

• 16-bit input/output timer

- 16-bit free run timer: 1 channel

- 16-bit input capture: (ICU): 4 channels

Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin

input.

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CAN controller: 1 channel

• Compliant with Ver2.0A and Ver2.0B CAN specifications

• 8 built-in message buffers

• Transmission rate of 10 Kbps to 1 Mbps (by 16 MHz machine clock)

• CAN wake-up

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UART (SCI): 1 channel

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available.

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