MB90495G Series
s
PRODUCT LINEUP
Part Number
Paarmeter
Feature Classification
ROM Size
RAM Size
Process
Package
Operating Power
Emulator power supply*
Number of instructions
Instruction bit length
Instruction length
Data bit length
: 351
: 8-bit, 16-bit
: 1 to 7 bytes
: 1 bit, 8-bit, 16-bit
MB90F497G
FLASH ROM
MB90497G
Mask ROM
2 Kbytes
CMOS
LQFP64 (width 0.65 mm) , QFP64 (width 1.0 mm)
4.5 V to 5.5 V
None
PGA256
MB90F498G
FLASH ROM
128 Kbytes
MB90V495G
Product Evaluated
6 Kbytes
64 Kbytes
CPU Functions
Minimum execution time : 62.5 ns (with 16-MHz machine clock)
Interrupt processing time : minimum 1.5
µs
(with 16-MHz machine clock)
Low-power consumption
(Standby) Mode
I/O Ports
Time-base timer
Sleep mode/watch mode/time-base timer mode/stop mode / CPU intermittent
mode
General-purpose I/O ports (CMOS output) : 49
18-bit free-run counter
Interrupt interval : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms
(with 4-MHz oscillation clock)
Reset generation intervals : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(with 4-MHz oscillation clock)
16-bit
Number of channels : 1
free-run timer Interrupts from overflow generation
Input capture
Number of channels : 4
Maintenance of free-run timer value through pin input (rising, falling or both edg-
es)
Number of channels : 2
16-bit reload timer operation
Count clock interval : 0.25
µs,
0.5
µs,
2.0
µs
(with 16-MHz machine clock)
External event count enabled
15-bit free-run counter
Interrupt intervals : 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s
(with 8.192-kHz subclock)
Number of channels : 2 (two 8-bit channels can be used)
Two 8-bit or one 16-bit channel PPG operation possible
Free interval, free duty pulse output possible
Count clock : 62.5 ns to 1
µs
(with 16-MHz machine clock)
Watchdog timer
16-bit
I/O Timer
16-bit reload timer
Watch timer
8/16-bit PPG timer
* : The S2 dipswitch setting when using the MB2145-507 emulation baud. For details, see the MB2145-507
hardware manual (2.7 Emulator Power Pin) .
(Continued)
4
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
