GL800AHU35 USB 2.0 UTMI Compliant Transceiver IP Core
TABLE OF CONTENTS
CHAPTER 1
CHAPTER 2
CHAPTER 3
GENERAL DESCRIPTION........................................................................ 6
FEATURES ................................................................................................... 7
BLOCK DIAGRAM..................................................................................... 8
3.1 S
YSTEM
C
ONFIGURATION
.............................................................................................. 8
3.2 B
LOCK
D
IAGRAM
........................................................................................................... 9
CHAPTER 4
PIN ASSIGNMENT.................................................................................... 11
4.1 P
INOUTS
....................................................................................................................... 11
4.2 P
IN
D
ESCRIPTIONS
....................................................................................................... 12
CHAPTER 5
FUNCTIONAL DESCRIPTION............................................................... 14
5.1 T
RANSMIT
O
PERATION
................................................................................................ 14
5.1.1 Transmit State Diagram..................................................................................... 14
5.1.2 Transmit Timing for Data Packet ..................................................................... 15
5.2 R
ECEIVE
O
PERATION
.................................................................................................. 15
5.2.1 Receive State Diagram ....................................................................................... 15
5.2.2 Receive Timing for Data Packet (with CRC-16).............................................. 16
5.3 T
IMING
C
HART
............................................................................................................ 17
5.3.1 CLKOUT Rising and Falling Edge VS. Input/Output Signals ...................... 17
5.3.2 Relationship Between Mode Change and Other Input Signals ...................... 18
CHAPTER 6 PACKAGE DIMENSION.......................................................................... 19
©2000-2003 Genesys Logic Inc.—All rights reserved.
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GENESYS [ GENESYS LOGIC ]
