GL9701 PCI Express
TM
to PCI Bridge
TABLE OF CONTENTS
CHAPTER 1 GENERAL DESCRIPTION.................................................... 9
CHAPTER 2 FEATURES ............................................................................ 10
2.1 PCI E
XPRESS
F
EATURES
........................................................................ 10
2.2 PCI I
NTERFACE
F
EATURES
................................................................... 10
2.3 P
OWER
M
ANAGEMENT
.......................................................................... 10
2.4 SMB
US
I
NTERFACE
............................................................................... 11
CHAPTER 3 PIN ASSIGNMENT ............................................................... 12
3.1 P
IN
C
ONFIGURATION
............................................................................. 12
3.2 P
IN
O
UT
.................................................................................................. 13
3.3N
UMERIC
P
IN
A
SSIGNMENT
L
IST
........................................................... 14
3.4 S
IGNAL
D
ESCRIPTION
............................................................................ 16
3.4.1 PCI-Express Interface.................................................................. 16
3.4.2 Secondary PCI Interface.............................................................. 17
3.4.3 EEPROM Signals ......................................................................... 18
3.4.4 Miscellaneous Signals ................................................................... 18
3.4.5 Power and Ground Signals .......................................................... 19
CHAPTER 4 BLOCK DIAGRAM............................................................... 21
CHAPTER 5 FUNCTION DESCRIPTION ................................................ 24
5.1 P
OWER
M
ANAGEMENT
.......................................................................... 24
5.1.1 PCI-PM Software Compatible Power Management .................. 24
5.1.2 Hardware-Controlled Active State Power Management............ 24
5.1.3 In-band Beacon............................................................................. 24
5.1.4 Side-band WAKE_N .................................................................... 25
5.1.5 Power Management System Messages ........................................ 25
5.2 PCI C
LOCK
R
UN
.................................................................................... 25
5.3 PCI C
LOCK
............................................................................................ 25
5.4 I
NTERRUPT MAPPING
............................................................................. 26
5.5 I
NITIAL
F
LOW
C
ONTROL
A
DVERTISEMENTS
......................................... 27
5.6 IDSEL M
APPING
................................................................................... 28
CHAPTER 6 REGISTER DESCRIPTION ................................................. 29
6.1 O
FFSET
00
H
: D
EVICE
I
DENTIFICATION
.................................................. 34
6.2 O
FFSET
04
H
: C
OMMAND
R
EGISTER
...................................................... 34
6.3 O
FFSET
06
H
: S
TATUS
R
EGISTER
............................................................ 35
©2000-2006
Genesys Logic Inc. - All rights reserved.
Page 4
GENESYS [ GENESYS LOGIC ]
