ERROR DETECTION
The errors detected and recorded in the STATUS register are
defined as follows:
TRANSMISSION ERROR
This error occurs whenever an incoming parity error is
detected and/or the GP521 detects that it is not synchronized
with the programming unit. This type of error sets a STATUS
bit and puts the circuit in unsynchronized mode. The
STATUS bit clears after a successful
read/write
operation.
BAD ADDRESS and / or OPERATION ERROR:
Status register is set when:
- any
write
operation is attempted while an EEPROM
write
is in progress
- a
write
operation is attempted on the ID register
- any operation is attempted on an unused address.
This type of error sets a STATUS bit and sets the parity bit of
the returned data stream to the incorrect value. This bit is
reset at the conclusion of a acceptable
read
or
write
operation.
COMMUNICATION FORMAT
The dialogue between the programming unit and the GP521
consists of 32 bits being sent to the GP521 which responds by
returning 16 bits to the programming unit. A complete dialogue
consisting of 48 bits as seen on the DATA line is as follows:
From Program Unit:
f
1
a
6
0
d
0
1
d
1
0
d
2
1
d
3
0
d
4
1
d
5
0
d
6
1
p
0
0
From GP521:
r
0
1
r
1
0
r
2
1
r
3
0
r
4
1
r
5
0
r
6
1
p
1
0
The dialogue begins with the bit
f
and ends with the two bits
p
1
,
0. The data and synchronization bits must be correct on the
falling edge of CLOCK. This relationship is shown in Figure 12.
1
a
0
0
a
1
1
a
2
0
a
3
1
a
4
0
a
5
DATA = 1010
where the final synchronization bit is a low. The next bit
following the 4 bit synch code is assumed to be part of a valid
dialogue. Once the GP521 is synchronized with the program
unit, it is possible to perform a continuous sequence of dia-
logues without having to re-synchronize unless transmission
errors occur. It is also possible to pause and continue the
transmission provided the proper relationship between CLOCK
and DATA is maintained.
To guarantee that the circuit synchronizes properly, the inter-
nal shift registers should be cleared by preceding the synch
code with a string of bits containing a synch error.
An example of the data sequence that guarantees a correctly
synchronized circuit is:
DATA = 11111010
p
1
The alternating 1’s and 0’s between information bits are used
to check whether the GP521 is synchronized with the
prgramming unit. The information bits are defined as:
f (function bit) f = 0
Write
data to specified memory
address
f = 1
Read
data from specified memory
address
a
6
a
5
a
4
a
3
a
2
a
1
a
0
d
6
d
5
d
4
d
3
d
2
d
1
d
0
p
O
7 bit address to read/write to
7 bit data to
write to
memory
parity bit for information from
program unit (odd parity)
7 bit data. If f=0, the data will echo the
7 bit data sent by the programming
unit. If f=1, the data is read from the
memory address.
Parity bit for data sent by GP521
(odd parity)
r
6
r
5
r
4
r
3
r
2
r
1
r
0
SYNCHRONIZATION OF THE GP521 WITH PROGRAMMER
The synchronization of the program with the GP521 is done
using a code in the data stream which cannot occur during a
correct dialogue. The GP521 looks for the following data
sequence in the data stream:
CLOCK
DATA
f
a
O
a
1
Synch bit alternates 1 0 1 0 1 ...
Fig. 12
7
510 - 79 - 06
GENNUM [ GENNUM CORPORATION ]
