GS4901B/GS4900B Preliminary Data Sheet
Table 3-12: GSPI Timing Parameters
Parameter
t
0
t
1
t
2
t
3
t
4
Definition
The minimum duration of time chip select, CS, must be
LOW before the first SCLK rising edge.
The minimum SCLK period.
Duty cycle tolerated by SCLK.
Minimum input setup time.
The minimum duration of time between the last SCLK
command word (or data word if the Auto-Increment bit is
HIGH) and the first SCLK of the data word (write cycle).
The minimum duration of time between the last SCLK
command word (or data word if the Auto-Increment bit is
HIGH) and the first SCLK of the data word (read cycle).
Minimum output hold time (15pF load).
The minimum duration of time between the last SCLK of
the GSPI transaction and when CS can be set HIGH.
Minimum input hold time.
Specification
1.5 ns
100 ns
40% to 60%
1.5 ns
37.1 ns
t
5
148.4 ns
t
6
t
7
t
8
1.5 ns
37.1 ns
1.5 ns
t
5
SCLK
CS
t
6
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDIN
SDOUT
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3-14: GSPI Read Mode Timing
t
0
SCLK
t
1
t
4
t
7
CS
t
3
R/W
RSV
RSV
AutoInc
A11
A10
t
2
A9
A8
A7
t
8
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIN
SDOUT
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3-15: GSPI Write Mode Timing
37703 - 0
April 2006
65 of 95
GENNUM [ GENNUM CORPORATION ]
