GS4901B/GS4900B Preliminary Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
Input_Standard
0Fh
0Fh
15-13
12
Reserved. Set these bits to zero when writing to 0Fh.
–
–
0
Force_Input - Set this bit HIGH to force the
GS4901B/GS4900B to recognize the applied input
reference format as the standard programmed in bits
11-6 of this register.
R/W
0Fh
11-6
Forced_Standard - When bit 12 is set HIGH, the
GS4901B/GS4900B will use the value programmed in
these bits, rather than the value in bits 5-0, to determine
the input reference format. The 6-bit value programmed
here should always correspond to the VID_STD[5:0]
value of the applied reference.
R/W
0
These bits should not be programmed for normal
operation.
0Fh
5-0
Detected_Standard - Contains the video standard
applied to the input reference pins once it has been
detected. These bits are set by the Reference Format
Detector block and correspond to the VID_STD[5:0]
value of the standard as listed in Table 1-2.
R/W
N/A
The Detected_Standard bits will be set to zero if no input
reference signal is applied or if the input reference
signal is not an automatically recognized video format.
Otherwise the value will be between 1 and 54.
Reference: Section 3.5.2 on page 43
Amb_Std_Sel
10h
10h
15-11
10-0
Reserved. Set these bits to zero when writing to 10h.
–
–
0
The user may set this register to distinguish between
different formats that look identical to the internal
Reference Format Detector block. See Table 3-2.
R/W
Reference: Section 3.5.2.1 on page 43
Reference_Standard_Disable
13h-11h
38-0
The Reference_Standard_Disable register may be used R/W
to disable/enable one or more of the input standards
given in Table 1-2 from being recognized by the device
and used to genlock the output. This is done by setting
the bit HIGH that corresponds to the VID_STD[5:0]
value of the video format.
FFFFh
FFFFh
F800h
For example, if bit 5 is set HIGH, then the output clock
and timing signals will not genlock to an input reference
with timing corresponding to VID_STD[5:0] = 5 in
Table 1-2.
Likewise, to enable recognition of VID_STD[5:0] = 26
(1080i/59.94) as an input reference format, the user
must set bit 26 LOW.
Address 13h = bits 38-32*
Address 12h = bits 31-16
Address 11h = bits 15-0
*Bits 47-39 of address 13h should always be written
HIGH.
Reference: Section 3.5 on page 42
RSVD
14h
–
Reserved
–
–
37703 - 0 April 2006
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