GS4901B/GS4900B Preliminary Data Sheet
4. Application Reference Design
4.1 GS4901B Typical Application Circuit
JTAG/HOSTb
SCLK
SDIN
SDOUT
CSb
VDD_IO
VDD_IO
10n
10n
1V8_VPLL
1V8_PCLK
10n
10n
GND_VPLL
22R
22R
PCLK1
PCLK2
RESETb
GENLOCKb
Controlled impedance
100-ohms differential
PCLK3
LOCK_LOST
REF_LOST
PCLK3b
1V8_PCLK
1V8_CORE
1V8_VPLL
VDD_IO
10n
10n
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LOCK_LOST
REF_LOST
VID_PLL_VDD
VID_PLL_GND
XTAL_VDD
X1
LVDS/PCLK3_GND
PCLK3
VDD_XTAL
10n
10n
3
PCLK3
4
GND_VPLL
27MHz
LVDS/PCLK3_VDD
CORE_VDD
5
38pF
24pF
6
22R
22R
22R
22R
22R
TIMING_OUT8
TIMING_OUT7
TIMING_OUT6
TIMING_OUT5
TIMING_OUT4
IO_VDD
TIMING8
TIMING7
TIMING6
TIMING5
TIMING4
7
1M
10n
X2
8
XTAL_GND
CORE_GND
ANALOG_VDD
NC
9
GS4901B
10
11
12
13
14
15
16
0R
1V8_APLL
GND_XTAL
22R
22R
22R
ANALOG_GND
AUD_PLL_GND
AUD_PLL_VDD
10FID
TIMING_OUT3
TIMING_OUT2
TIMING_OUT1
ASR_SEL0
TIMING3
TIMING2
TIMING1
GND_XTAL
10n
HSYNC
ASR_SEL1
GND_APLL
The 10FID input must be
grounded if it will not be used
65
GND_PAD
10FID
HSYNC
VSYNC
FSYNC
22R
22R
22R
ACLK1
ACLK2
ACLK3
VDD_IO
1V8_CORE
10n
10n
NOTE: The GS4911A inputs are 5V tolerant for
3V3 I/O operation only (IO_VDD=3V3)
10n
VID_STD0
VID_STD1
VID_STD2
VID_STD3
ASR_SEL0
ASR_SEL1
ASR_SEL2
NOTE: For a solution with the lowest output jitter, the GS9062 or GS9092A
serializers are recommended for use with the GS4901B/GS4900B.
37703 - 0 April 2006
89 of 95
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