GS9002A PIN DESCRIPTIONS
NOT RECOMMENDED FOR NEW DESIGNS
PIN NO.
1
2
3
SYMBOL
V
EE
V
CC3
SYNC DET.
TYPE
DESCRIPTION
Power Supply: Most negative power supply connection.
Power Supply: Most positive power supply connection for the PLL and scrambler.
O
TTL output level that detects the occurrence of all zero’s or all one’s at inputs PD2-PD9
and pulses LOW for three PCK-IN durations. Used to detect SMPTE 259M reserved words
(000-003 and 3FC-3FF) in TRS sync word. Parallel data bits PD0 and PD1 are set Low or
High when PD2 - PD9 are Low or High respectively.
Power Supply: Most negative power supply connection.
Power Supply: Most positive power supply connection for the input data latches and serializer.
4
5
6
7-16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
EE
V
CC1
SYNC DET.
DISABLE
PD0-PD9
PCK-IN
V
EE
PCK OUT
LOCK DET.
V
CC3
LOOP FILT.
V
EE
NC
V
EE
SSS
V
EE
V
CC3
C
REG
V
EE
R
VCO3
I
I
I
I
O
O
I
I
I
TTL level input that disables the internal Sync Detector when HIGH. This allows the
GS9002 to serialize 8 or 10 bit non - SMPTE Standard parallel data.
TTL level inputs of the parallel data words. PD0 is the LSB and PD9 is the MSB.
TTL level input of the Parallel Clock.
Power Supply: Most negative power supply connection.
Pseudo-ECL output representing the re-clocked Parallel Clock and is derived from the
internal VCO. The VCO is divided by 10 in order to produce this output.
TTL level output which goes HIGH when the internal PLL is locked.
Power Supply: Most positive power supply connection for the PLL and scrambler.
Connection for the R-C loop filter components. The loop filter sets the PLL loop
parameters.
Power Supply: Most negative power supply connection.
Power Supply: Most negative power supply connection.
Scrambler/Serializer Select. TTL level input that selects scrambled NZRI output when
logic LOW or direct serializer output when logic HIGH.
Power Supply: Most negative power supply connection.
Power Supply: Most positive power supply connection for the PLL and scrambler.
Compensation RC network for internal voltage regulator that requires decoupling with a series
0.1µF capacitor and 820Ω resistor. Components should be located as close as possible to the pin.
Power Supply: Most negative power supply connection.
VCO Resistor 3: Analog current input used to set the centre frequency of the VCO when
the two Data Rate Select bits (pins 35 and 36) are both set to logic 1. A resistor is
connected from this pin to V
EE
.
VCO Resistor 2: Analog current input used to set the centre frequency of the VCO when
the Data Rate Select Bit 0 (pin 36) is set to logic 0 and the Data Rate Select Bit 1 (pin 35)
is set to logic 1. A resistor is connected from this pin to V
EE
.
VCO Resistor 1: Analog current input used to set the centre frequency of the VCO when
the Data Rate Select Bit 0 (pin 36) is set to logic 1 and the Data Rate Select Bit 1 (pin 35)
is set to logic 0. A resistor is connected from this pin to V
EE
.
VCO Resistor 0: Analog current input used to set the centre frequency of the VCO when
the two Data Rate Select bits (pins 35 and 36) are both set to logic 0. A resistor is
connected from this pin to V
EE
.
TTL level inputs to the internal 2:4 demultiplexer used to select one of four VCO frequency
setting resistors (R
VCO0
- R
VCO3
). (See above)
32
R
VCO2
I
33
R
VCO1
I
34
R
VCO0
I
35,36
DRS0, 1
I
5 of 11
24149 - 1
GENNUM [ GENNUM CORPORATION ]
