110
CHIP DISABLED CROSSTALK (dB)
90
CHIP DISABLED CROSSTALK (dB)
100
110
100
Analog signal
IN is 40 IRE
(286 mV p-p)
at 10 MHz
90
80
70
60
50
10
100
80
-1
0
+1
+2
+3
FREQUENCY (MHz)
INPUT BIAS (V)
Chip Disabled Crosstalk vs Frequency
Chip Disabled Crosstalk vs Input Bias (V)
DIFFERENTIAL PHASE & GAIN (DEGREES & %)
+0.05
+0.04
+0.03
+0.02
+0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.8
-0.2
ƒ = 3.58 MHz
Blanking level is
clamped to V
BIAS
DIFFERENTIAL PHASE & GAIN (DEGREES & %)
+0.05
Blanking level
0V DC
dg
%
+0.04
dg
%
+0.03
dp
°
+0.02
dp
°
+0.01
-0.6
-0.4
0
+0.2
+0.4
+0.6
+0.8
0
1
2
3
3.58
4
5
8
10
INPUT BIAS (V)
dg/dp
vs Input Bias
FREQUENCY (MHz)
dg
/
dp
vs Frequency
30 MΩ
+1.0
+0.8
10 MΩ
4
GAIN SPREAD (dB)
+0.4
+0.2
0.1
-0.2
-0.4
-0.6
-0.8
-1.0
0.1
1
10
100
R
IN ON
1 MΩ
C
IN OFF
100 kΩ
C
IN ON
2
3
10 kΩ
-1
0
+1
+2
+3
1
FREQUENCY (MHz)
INPUT BIAS (V)
Normalized Gain Spread C
L
= 30pF
Input Impedance
5
510 -34 -2
INPUT CAPACITANCE (pF)
+0.6
R
IN OFF
GAIN SPREAD (dB)
INPUT CAPACITANCE (pF)