2.
Load Resistance Considerations
3. Multi-chip Considerations
Whenever multi-chip bus systems are to be used, the total
input and output capacitance must be carefully considered.
The input capacitance of an enabled crosspoint (chip selected),
is typically only 2 pF and increases slightly to 2.4 pF when the
chip is disabled. The total output capacitance when the chip
is disabled is approximately 15 pF per chip.
Usually the GX434 multiplexer switch is used in a matrix
configuration of (n x 1) crosspoints perhaps combined in an
(n x m) total routing matrix. This means for example, that four
ICs produce a 16 x 1 configuration and have a total output
capacitance of 4 x15 pF or 60 pF if all four chips are disabled.
For any one enabled crosspoint, the effective load capacitance
will be 3 x15 pF or 45 pF.
In a multi-input/multi-output matrix, it is important to consider
the total input bus capacitance. The higher the bus capacitance
and the more it varies from the ON to OFF condition, the more
difficult it is to maintain a wide frequency response and
constant drive from the input buffer. A 16 x 16 matrix using 64
ICs (16 x 4), would have a total input bus capacitance of 16 x
2.4 pF or 40 pF.
The GX434 crosspoint switch is optimised for load resistances
equal to or greater than 3 kΩ. Figure 8 shows the effect on the
differential gain and phase when the load resistance is varied
from 100
Ω
to 100 kΩ.
DIFFERENTIAL PHASE & GAIN (DEGREES & %)
10
ƒ= 3.58 MHz, 20 IRE
BLANKING LEVEL = 0V DC
1.0
0.1
dp
dg
0.01
0.001
100
1K
10K
100K
R
L
(Ω)
Fig. 8
dg/dp
vs R
L
The negative slew rate is dependant upon the output current
and load capacitance as shown below.
-SR =
I +
3 mA
I
≤
8 mA
C
L
The current
I
is determined from the following equation:
I
= -V
EE
R
≥
1k
Ω
R
It is possible to increase the negative slew rate (-S.R.) and thus
the large signal bandwidth, by adding a resistance from the
output to - V
EE
. This resistor increases the output current above
the 3 mA provided by the internal current generator and
increases the negative slew rate. The additional slew rate
improving resistance must not be less than 1kΩ in order to
prevent excessive currents in the output of the device. An
adverse effect of utilising this negative slew rate improving
resistor, is the increase in differential phase from typically
0.009° to 0.014°. Under these same conditions, the differential
gain drops from typically 0.033 % to 0.021 %.
+8V
1
2
3
4
X
G
4
41
X
G
4
41
X
G
4
41
X
G
4
41
BUFFERS
5
6
7
8
X
G
4
41
X
G
4
41
X
G
4
41
X
G
4
41
INPUT
9
10
11
12
X
G
4
41
X
G
4
41
X
G
4
41
X
G
4
41
IN 0
GND
IN 1
GND
IN 2
GND
IN 3
1
2
3
4
5
6
7
14
13
12
A1
11
10
9
8
NC
R
≥
1kΩ
CS
OUTPUT
A0
n
O U TP U
T
B U FF E
R S
1
2
3
m
-8V
Fig.9
Negative Slew Rate (-SR) Improvement
Fig.10 Multi-chip Connections
510 -34 -2
8
GENNUM [ GENNUM CORPORATION ]
