GS72116AJ-10I 参数 Datasheet PDF下载

GS72116ATP/J/T/U

Read Cycle 2: WE = V

IH

tRC

Address

tAA

CE

tAC

tLZ

UB, LB

OE

tBLZ

tOE

Data Out

tOLZ

High impedance

tAB

tBHZ

tOHZ

Data valid

tHZ

Write Cycle

Parameter

Write cycle time

Address valid to end of write

Chip enable to end of write

Byte enable to end of write

Data set up time

Data hold time

Write pulse width

Address set up time

Write recovery time (WE)

Write recovery time (CE)

Output Low Z from end of write

Write to output in High Z

Symbol

tWC

tAW

tCW

tBW

tDW

tDH

tWP

tAS

tWR

tWR1

tWLZ

*

tWHZ

*

-7

Min

7

5

5

5

3.5

0

5

0

0

0

3

—

Max

—

—

—

—

—

—

—

—

—

—

—

3

Min

8

5.5

5.5

5.5

4

0

5.5

0

0

0

3

—

-8

Max

—

—

—

—

—

—

—

—

—

—

—

3.5

Min

10

7

7

7

5

0

7

0

0

0

3

—

-10

Max

—

—

—

—

—

—

—

—

—

—

—

4

Min

12

8

8

8

6

0

8

0

0

0

3

—

-12

Max

—

—

—

—

—

—

—

—

—

—

—

5

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

* These parameters are sampled and are not 100% tested.

Rev: 1.04a 10/2002

8/18

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.