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GS74116J-12I 参数 Datasheet PDF下载

GS74116J-12I图片预览
型号: GS74116J-12I
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×16的4Mb SRAM的异步 [256K x 16 4Mb Asynchronous SRAM]
分类和应用: 静态存储器
文件页数/大小: 14 页 / 134 K
品牌: GSI [ GSI TECHNOLOGY ]
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GS74116TP/J/U
AC Characteristics
Read Cycle
Parameter
Read cycle time
Address access time
Chip enable access time (CE)
Byte enable access time (UB, LB)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Byte enable to output in low Z (UB, LB)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Byte disable to output in High Z (UB, LB)
Symbol
t
RC
t
AA
t
AC
t
AB
t
OE
t
OH
t
LZ
*
t
OLZ
*
t
BLZ
*
t
HZ
*
t
OHZ
*
t
BHZ
*
-8
Min
8
---
---
---
---
3
3
0
0
---
---
---
-10
Max
---
8
8
3.5
3.5
---
---
---
---
4
3.5
3.5
-12
Min
12
---
---
---
---
3
3
0
0
---
---
---
-15
Min
15
---
---
---
---
3
3
0
0
---
---
---
Min
10
---
---
---
---
3
3
0
0
---
---
---
Max
---
10
10
4
4
---
---
---
---
5
4
4
Max
---
12
12
5
5
---
---
---
---
6
5
5
Max
---
15
15
6
6
---
---
---
---
7
6
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* These parameters are sampled and are not 100% tested
Read Cycle 1: CE = OE = V
IL
, WE = V
IH
, UB and, or LB = V
IL
t
RC
Address
t
AA
t
OH
Data Out
Previous Data
Data valid
Rev: 2.02 3/2000
6/14
© 1999, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.